1. Field of the Invention
This invention relates to microprocessor architecture and, more particularly, to an immediate and displacement decode mechanism.
2. Description of the Related Art
In various systems, the front end of a processor core typically includes an instruction decode unit for decoding instructions that are fetched from the instruction cache before being sent to the execution unit. Besides the actual instruction bits, fetched instructions usually have one or more constants that are used, for example, by the execution unit to process the instructions. For instance, in some systems, fetched instructions may include immediate or displacement (imm/disp) constants.
In typical processors, to perform the decode operation, the instruction decode unit may retrieve the actual instructions from a first buffer and ignore the constants. After the instructions are decoded, the decoded instructions are stored in a second buffer. When a decoded instruction is ready to be sent to the execution unit, a steer unit usually retrieves the constants from the first buffer and provides the constants to the execution unit at approximately the same time the instruction decode unit provides the corresponding decoded instruction to the execution unit.
In these systems, the first buffer typically needs to be relatively large in size, since it has to reserve space for the constants until the corresponding instruction is decoded and ready to be sent to the execution unit. In other words, in some cases, the constants may need to be stored in the first buffer for several clock cycles. The relatively large size of the first buffer may increase die area and cost of the processor.